Updated September 2026. This article first appeared in December 2024, when 2nm was still in trial production. It has been rewritten to explain the CyberShuttle service properly and to reflect that TSMC's 2nm process is now in volume production.
Before a company commits to building a chip in volume, it wants silicon in hand to prove the design works. At the leading edge that proof is expensive, because the mask set alone costs a fortune and a single wafer is not cheap either. TSMC's answer is a shared prototyping run it calls CyberShuttle.
How a shuttle run works
CyberShuttle is TSMC's multi-project wafer (MPW) service (TSMC). The idea is common across the foundry industry:
- Several customers book space on the same shuttle and submit their test-chip designs.
- The foundry places all of those designs onto one shared mask set.
- The wafers are processed once, and each customer receives the dies carrying its own design.
Because the mask and wafer costs are split between everyone on the shuttle, each customer pays far less than it would for a dedicated run, and can verify its design before paying for a full production mask set (Tower Semiconductor's description of MPW shuttles).
Anyone from manufacturing will recognise the logic. It is the same reason prototype parts are often grouped onto one shared tooling or build run: the fixed cost of setting up is the expensive part, so you spread it across as many parts as you can. The trade-off is also familiar. You get a small number of prototype dies on the foundry's schedule, not a volume supply on yours.
How is a shuttle run different from a production run?
The two serve different purposes, and the differences explain why companies use both:
| Shuttle (MPW) run | Dedicated production run | |
|---|---|---|
| Mask set | Shared with other customers | Owned by one customer |
| Mask and wafer cost | Split between everyone on the shuttle | Paid in full by one customer |
| Number of chips | Small quantity of prototype dies | Full wafers, scaled to demand |
| Schedule | Fixed dates set by the foundry | Set around the customer's plan |
| Purpose | Prove the design, measure real silicon | Supply finished products |
A typical path is one or more shuttle runs to validate a design and fix problems, then a full mask set once the design is right. Finding a bug at the shuttle stage costs a fraction of finding it after a production mask set has been paid for.
Why it matters more at 2nm
Every new node raises the cost of getting a design onto silicon. Reporting in late 2024 put the cost of a single 2nm wafer at around $30,000 (Wccftech). At that price, sharing a run is the difference between a smaller design house testing on 2nm or skipping it. I worked through what that wafer price and yield mean for the cost of each good chip in what TSMC's 2nm yield actually means for the chips you'll buy. Reports in 2024 described TSMC scheduling 2nm shuttle runs for customers ahead of volume production (TrendForce).
What changed with the transistor
TSMC's 2nm (N2) node is its first to use nanosheet, or gate-all-around (GAA), transistors. In the older FinFET design the gate wraps a vertical fin on three sides. In a nanosheet transistor, horizontal sheets of silicon are stacked and the gate surrounds each one completely, which gives better control of current and less leakage. TSMC quotes N2 at 10 to 15 percent more speed at the same power than its N3E 3nm process, or 25 to 30 percent less power at the same speed (Focus Taiwan).
Where 2nm stands in 2026
- Trial production: in December 2024, reports said TSMC's 2nm trial yields had passed 60 percent (TrendForce).
- Volume production: TSMC began 2nm volume production in the fourth quarter of 2025, centred on Fab 22 in Kaohsiung (Focus Taiwan, Tom's Hardware).
- Next step: the enhanced N2P process is slated for volume production in the second half of 2026.
- Competition: Samsung announced the Exynos 2600 in December 2025 as the first 2nm smartphone chip (GSMArena).
What I would watch
Yield figures in the press come from unnamed sources and are measured in different ways, so I treat any single percentage with caution. The more useful signal is the one this article is really about: how many smaller designers can afford to get onto the node at all. Shuttle programmes are what make that possible, and they tend to get less attention than the headline chips from the largest customers. For the wider picture of who supplies each step, from lithography machines to packaging, see semiconductor supply chain 2026: who makes what.
Related gear
- Chip War (Chris Miller) on Amazon — Related gear
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FAQ
What does CyberShuttle cost?
TSMC does not publish shuttle prices. The cost depends on the process node, the area each customer books on the shared mask and the number of dies requested. The saving comes from splitting mask and wafer costs between participants rather than paying for a full mask set alone.
Who uses shuttle runs?
Chip design companies of every size, universities and research groups. Large companies use them to test new ideas or IP blocks early; smaller ones may use them because a dedicated mask set at the leading edge is simply too expensive.
Is CyberShuttle only for 2nm?
No. TSMC runs shuttles across many of its process technologies. The 2nm runs attracted attention because they gave customers an early chance to test designs on the new nanosheet transistors before volume production.
Can a shuttle chip be sold as a product?
Generally no. Shuttle runs produce a limited number of prototype dies for testing and evaluation. Products are built from dedicated production runs once the design is proven.
